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SY89859U
Precision Low-Power 8:1 MUX with Internal Termination and 1:2 LVPECL Fanout Buffer
General Description
The SY89859U is a low jitter, low-power, high-speed 8:1 multiplexer with a 1:2 differential fanout buffer optimized for precision telecom and enterprise server distribution applications. The SY89859U distributes clock frequencies from DC to >2.5GHz, and data rates to 2.5Gbps guaranteed over temperature and voltage. The SY89859U differential input includes Micrel's unique, 3-pin input termination architecture that directly interfaces to any differential signal (AC- or DC-coupled) as small as 100mV (200mVpp) without level shifting or termination resistor networks in the signal path. The outputs are 800mV, 100K-compatible LVPECL with extremely fast rise/fall time guaranteed to be less than 180ps. The SY89859U features a patent-pending isolation design that significantly improves on channel-tochannel crosstalk-induced jitter performance. The SY89859U operates from a 2.5V 5% or 3.3V 10% supply and is guaranteed over the full industrial temperature range of -40C to +85C. The SY89859U is part of Micrel's high-speed, Precision Edge(R) product line. All support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge(R)
Features
* Selects between 1 of 8 inputs, and provides 2 precision, low skew 100K-compatible LVPECL output copies * Low power: 150mW typ. (2.5V) * Guaranteed AC performance over temperature and voltage: - DC to >2.5Gbps - DC to >2.5GHz - <690ps propagation delay - <180ps tr/tf time - <20ps skew (output-to-output) * Unique, patent-pending channel-to-channel isolation design provides superior crosstalk performance * Ultra-low jitter design: - <1psRMS random jitter - <10psPP deterministic jitter - <10psPP total jitter (clock) - <1psRMS cycle-to-cycle jitter - <0.7psRMS crosstalk-induced jitter * Unique, patented input termination and VT pin accepts DC- and AC-coupled inputs (CML, PECL, LVDS) * Power supply 2.5V 5% or 3.3V 10% * -40C to +85C industrial temperature range * Available in 44-pin (7mm x 7mm) MLF(R) package
Applications
* * * *
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
Data communication systems All SONET/SDH data/clock applications All Fibre Channel applications All Gigabit Ethernet applications
February 2007
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Micrel, Inc.
SY89859U
Functional Block Diagram
February 2007
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SY89859U
Ordering Information(1)
Part Number SY89859UMG SY89859UMGTR(2)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel.
Package Type MLF-44 MLF-44
Operating Range Industrial Industrial
Package Marking SY89859U with Pb-Free bar-line indicator SY89859U with Pb-Free bar-line indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
44-Pin MLF(R) (MLF-44)
Truth Table
SEL2 L L L L H H H H SEL1 L L H H L L H H SEL0 L H L H L H L H Q IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 /Q /IN0 /IN1 /IN2 /IN3 /IN4 /IN5 /IN6 /IN7
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SY89859U
Pin Description
Pin Number 20, 18 16, 14 13, 11 9, 7 5, 3 1, 43 42, 40 38, 36 19, 15 12, 8 4, 44 41, 37 17 10 2 39 21 22 35 24, 27, 29, 32 25, 26 30, 31 23, 28, 33 Pin Name IN0, /IN0 IN1, /IN1 IN2, /IN2 IN3, /IN3 IN4, /IN4 IN5, /IN5 IN6, /IN6 IN7, /IN7 VT0, VT1 VT2, VT3 VT4, VT5 VT6, VT7 VREF-AC0 VREF-AC1 VREF-AC2 VREF-AC3 SEL0 SEL1 SEL2 VCC Q0, /Q0 Q1, /Q1 GND Exposed Pad Pin Function Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-coupled signals as small as 100mV (200mVpp). Each pin of a pair internally terminates to a VT pin through 50. Note that these inputs will default to an indeterminate state if left open. Please refer to the "Input Interface Applications" section for more details. Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VT pins provide a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" section for more details. For a CML or LVDS inputs, the VT pin is left floating. Reference Voltage: These outputs bias to VCC-1.2V. They are used when AC coupling the inputs (IN, /IN). For AC-coupled applications, connect VREF-AC to the VT pin and bypass with a 0.01F low ESR capacitor to VCC. See "Input Interface Applications" section for more details. The single-ended TTL/CMOS-compatible inputs select the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to a logic HIGH state if left open. The threshold voltage is VTH = VCC/2. Positive Power Supply. Bypass with 0.1F||0.01F low ESR capacitors and place as close to each VCC pin as possible. Differential Outputs: These 100K-compatible LVPECL output pairs are the outputs of the device. Unused output pairs may be left open. Each output is designed to drive 800mV into 50 terminated to VCC-2V. Ground. GND and exposed pad must both be connected to the same ground plane.
February 2007
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SY89859U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) .......................... -0.5V to +4.0V Input Voltage SEL0, SEL1, SEL2 .......................... -0.5V to VCC IN0, /IN0, IN1, /IN1,.../IN7, /IN7 ...... -0.5V to VCC LVPECL Output Current (IOUT) Continuous................................................50mA Surge ......................................................100mA Termination Current Source or sink current VT0, VT1, VT2,...VT7.............................100mA Input Current Source or sink current IN0, /IN0, IN1, /IN1,...IN7, /IN7 ................50mA VREF Output Current VREF-AC0, VREF-AC1..., VREF-AC3.......2mA Lead Temperature (soldering, 20 sec.) .......... +260C Storage Temperature (Ts) ................. -65C to 150C
Operating Ratings(2)
Supply Voltage (VCC).................. +2.375V to +2.625V .................................................+3.0V to +3.6V Ambient Temperature (TA)................ -40C to +85C Package Thermal Resistance(3) MLF(R) (JA) Still-Air ................................................ 24C/W MLF(R) (JB) Junction-to-Board ............................... 12C/W
DC Electrical Characteristics(4)
TA = -40C to +85C, unless otherwise stated.
Symbol VCC ICC RIN RDIFF_IN VIH VIL VIN VDIFF_IN VT_IN VREF-AC
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still-air, unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Power Supply Power Supply Current Input Resistance (IN-to-VT) Differential Input Resistance (IN-to-/IN) Input High Voltage (IN, /IN) Input Low Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing |IN-to-/IN| IN-to-VT (IN, /IN) Output Reference Voltage
Condition
Min 2.375 3.0
Typ 2.5 3.3 60 50 100
Max 2.625 3.6 85 55 110 VCC VIH-0.1 1.7
Units V V mA V V V V
No load, max. VCC 45 90 VCC-1.2 0 See Figure 1a. See Figure 1b. 0.1 0.2
1.28 VCC-1.3 VCC-1.2 VCC-1.1
V V
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SY89859U
100K LVPECL Output DC Electrical Characteristics(6)
VCC = +2.5V 5% or 3.3V 10%, RL = 50 to VCC-2V; TA = -40C to +85C, unless otherwise stated.
Symbol VOH VOL VOUT VDIFF_OUT Parameter Output HIGH Voltage (Q, /Q) Output LOW Voltage (Q, /Q) Output Differential Swing Differential Output Voltage Swing See Figure 1a. See Figure 1b. Condition Min VCC-1.145 VCC-1.945 550 1100 800 1600 Typ Max VCC-0.895 VCC-1.695 Units V V mV mV
LVTTL/CMOS DC Electrical Characteristics(6)
VCC = +2.5V 5% or 3.3V 10%; TA = -40C to +85C, unless otherwise stated.
Symbol VIH VIL IIH IIL
Note: 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0
Typ
Max 0.8
Units V V A A
IIH @ VIN = VCC IIL @ VIN = 0.5V
-125 -300
40
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SY89859U
AC Electrical Characteristics(7)
VCC = +2.5V 5% or 3.3V 10%; VIN 100mV (200mVpp); RL = 50 to VCC-2V; TA = -40C to +85C, unless otherwise stated.
Symbol fMAX Parameter Maximum Operating Frequency Differential Propagation Delay tpd tpd Tempco tSKEW IN-to-Q SEL-to-Q Differential Propagation Delay Temperature Coefficient Output-to-Output Skew Part-to-Part Skew Data Random Jitter (RJ) Deterministic Jitter (DJ) tJITTER Clock Cycle-to-Cycle Jitter Total Jitter (TJ) Adjacent Channel Crosstalk-induced Jitter tr, tf
Notes: 7. 8. 9. High-frequency AC-parameters are guaranteed by design and characterization. Output-to-output skew is measured between two different outputs under identical input transitions. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs.
23
Condition
Min 2.5 2.5 360 200
Typ 3.5 475 600 300 400
Max
Units Gbps GHz
640 850
ps ps fs/oC
IN-to-Q SEL-to-Q Note 8 Note 9 Note 10 Note 11 Note 12 Note 13 Note 14 At full output swing. 50 5
20 200 1 10 1 10 0.7 110 180
ps ps psRMS psPP psRMS psPP psRMS ps
Output Rise/Fall Time (20% to 80%)
10. Random jitter is measured with a K28.7 character pattern, measured at 12
Single-Ended and Differential Swings
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
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SY89859U
Typical Operating Characteristics
VCC = 3.3V, GND = 0, VIN = 100mV (200mVpp), RL = 50 to VCC-2V; TA = 25C, unless otherwise stated.
February 2007
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SY89859U
Functional Characteristics
VCC = 3.3V, GND = 0, VIN = 100mV (200mVpp), RL = 50 to VCC-2V; TA = 25C, unless otherwise stated.
February 2007
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SY89859U
Input and Output Stages
Figure 2a. Simplified Differential Input Stage
Figure 2b. Simplified LVPECL Output Stage
Input Interface Applications
Option: may connect VT to VCC Figure 3a. LVPECL Interface (DC-Coupled) Figure 3b. LVPECL Interface (AC-Coupled) Figure 3c. CML Interface (DC-Coupled)
Figure 3d. CML Interface (AC-Coupled)
Figure 3e. LVDS Interface
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SY89859U
LVPECL Output Interface Applications
LVPECL has high input impedance, very low output (open emitter) impedance, and small signal swing which result in low EMI. LVPECL is ideal for driving 50- and 100-controlled impedance transmission lines. There are several techniques for terminating the LVPECL output including: Parallel TerminationThevenin Equivalent, Parallel Termination (3Resistor), and AC-Coupled Termination. Unused output pairs may be left floating. However, singleended outputs must be terminated, or balanced.
Figure 4a. Parallel Thevenin-Equivalent Termination
Note: For 2.5V system, R1 = 250, R2 = 62.5. Note:
Figure 4b. Parallel Termination (3-Resistor)
For 2.5V system, Rb = 19.
Related Product and Support Documentation
Part Number SY58037U SY58038U SY58039U Function Ultra Precision 8:1 MUX with Internal Termination and 1:2 CML Fanout Buffer Ultra Precision 8:1 MUX with Internal Termination and 1:2 LVPECL Fanout Buffer Ultra Precision 8:1 MUX with Internal Termination and 1:2 400mV LVPECL Fanout Buffer New Products and Applications MLF Application Note
(R)
Data Sheet Link http://www.micrel.com/product-info/products/sy58037u.shtml http://www.micrel.com/product-info/products/sy58038u.shtml http://www.micrel.com/product-info/products/sy58039u.shtml
HBW Solutions
www.micrel.com/product-info/products/solutions.shtml www.amkor.com/products/notes_papers/MLFAppNote.pdf
February 2007
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Micrel, Inc.
SY89859U
Package Information
44-Pin MLF(R) (MLF-44)
PCB Thermal Consideration for 44-Pin MLFTM Package (Always solder, or equivalent, the exposed pad to the PCB)
Package Notes: 1. 2. 3. Package meets Level 2 qualification. All parts are dry-packaged before shipment. Exposed pads must be soldered to a ground for proper thermal management.
February 2007
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Micrel, Inc.
SY89859U
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated.
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